Dual-damascene interconnect features are advantageously used to provide planarized interconnect structures that afford the use of multiple interconnect layers and therefore increase levels of device integration. There is a trend in the semiconductor industry towards the use of low-dielectric constant (low-k) dielectric materials, particularly used in conjunction with copper conductive lines, to reduce the RC time delay of the conductive lines. Dual-damascene methods include either a “via-first” patterning methods in which via holes are first patterned in the insulating layer through the entire thickness of the insulating layer, and then trenches are patterned in a top portion of the insulating layer. Or, the trenches may alternatively be patterned in a top portion of the insulating layer first, followed by the patterning of the via holes through the insulating layer, called “trench-first” patterning methods. However, the two approaches need separated etching steps for forming the trench and via hole. It remains a challenge in dual damascene process to develop simplified processing with fewer processing steps, both photo and etching steps, to achieve the trench/via patterning and formation of trench and via holes.